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(R)
EL4543
Data Sheet July 8, 2004 FN7325.2
Triple Differential Twisted-Pair Driver with Common-Mode Sync Encoding
The EL4543 is a high bandwidth triple differential amplifier with integrated encoding of video sync signals. The inputs are suitable for handling high speed video or other communications signals in either single-ended or differential form, and the common-mode input range extends all the way to the negative rail enabling groundreferenced signalling in single supply applications. The high bandwidth enables differential signalling onto standard twisted-pair or coax with very low harmonic distortion, while internal feedback ensures balanced gain and phase at the outputs reducing radiated EMI and harmonics. Embedded logic encodes standard video horizontal and vertical sync signals onto the common mode of the twisted pair(s), transmitting this additional information without the requirement for additional buffers or transmission lines. The EL4543 enables significant system cost savings when compared with discrete line driver alternatives. The EL4543 is available in a 24-pin QSOP package and is specified for operation over the -40C to +85C temperature range.
Features
* Fully differential inputs, outputs, and feedback * 350MHz -3dB bandwidth * 1200V/s slew rate * -75dB distortion at 5MHz * Single 5V to 12V operation * 50mA minimum output current * Low power - 36mA total typical supply current * Pb-free available
Applications
* Twisted-pair driver * Differential line driver * VGA over twisted-pair * Transmission of analog signals in a noisy environment
TABLE 1. SYNC SIGNAL ENCODING COMMON MODE A (RED) 3.0 2.5 2.0 2.5 COMMON MODE B (GREEN) 2.0 3.0 3.0 2.0 COMMON MODE C (BLUE) 2.5 2.0 2.5 3.0
H Low Low
V High Low Low High
Ordering Information
PART NUMBER EL4543IU EL4543IU-T7 EL4543IU-T13 EL4543IUZ (Note 1) EL4543IUZ-T7 (Note 1) EL4543IUZ-T13 (Note 1) EL4543IL (Note 2) NOTES: 1. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. 2. Coming soon PACKAGE 24-Pin QSOP 24-Pin QSOP 24-Pin QSOP 24-Pin QSOP (Pb-Free) 24-Pin QSOP (Pb-Free) 24-Pin QSOP (Pb-Free) 20-Pin QFN TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0046
High High
TABLE 2. INPUT LOGIC THRESHOLD (+5V SUPPLY) VLO, max VHI, min 0.8V 2V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL4543 Pinouts
EL4543 (24-PIN QSOP) TOP VIEW
EN 1 VINA+ 2 VINA- 3 NC 4 VSYNC 5 HSYNC 6 NC 7 VINB+ 8 VINB- 9 NC 10 VINC+ 11 VINC- 12 + + + 24 VOUTA+ 23 VOUTA22 NC 21 VS+ 20 VS19 NC 18 VOUTB+ 17 VOUTB16 NC 15 VOUTC+ 14 VOUTC13 NC *COMING SOON VSYNC 1 HSYNC 2 NC 3 VINB+ 4 VINB- 5 VOUTC+ 10 VINC+ 6 VINC- 7 NC 8 VOUTC- 9 THERMAL PAD
EL4543 (20-PIN QFN*) TOP VIEW
17 VOUTA+ 16 VOUTA15 VS+ 14 VS13 NC 12 VOUTB+ 11 VOUTB19 VINA+
20 VINA-
2
18 ENB
EL4543
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VS+ & VS-). . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . 70mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . . -40C to +85C VIN+, VINB . . . . . . . . . . . . . . . VS- + 0.8V (min) to VS+ - 0.8V (max) VIN- - VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW (-3dB) SR TSTL GBW HD2 HD3 dP dG -3dB Bandwidth
VS+ = +5V, VS- = 0V, TA = 25C, VIN = 0V, RL = 150, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
VOUT = 2VP-P RL = 200 600
350 750 13.6 700 1200
MHz V/s ns MHz dBc dBc %
Differential Slew Rate Settling Time to 0.1% Gain Bandwidth Product 2nd Harmonic Distortion 3rd Harmonic Distortion Differential Phase @ 3.58MHz Differential Gain @ 3.58MHz
f = 20MHz, RL = 200 f = 20MHz, RL = 200
-70 -70 0.01 0.01
INPUT CHARACTERISTICS VOS IIN ZIN VDIFF VCM VN CMRR EN Input Referred Offset Voltage Input Bias Current (VIN+, VIN+) Differential Input Impedance Differential Input Range Input Common Mode Voltage Range Input Referred Voltage Noise Input Common Mode Rejection Ratio Threshold VCM = 0 to 2V 60 0 27 80 1.4 -10 -25 2 -15 180 0.75 3.2 10 -10 mV A k V V nV/Hz dB V
OUTPUT CHARACTERISTICS IOUT Output Peak Current 40 60 mA
DC PERFORMANCE AV Voltage Gain VIN = 0.8VP-P 1.82 1.89 1.99 V/V
SUPPLY CHARACTERISTICS VSUPPLY IS PSRR Supply Operating Range Power Supply Current (per Channel) Power Supply Rejection Ratio VS+ to VS5 10.8 70 13 80 12 14.6 V mA dB
3
EL4543 Pin Descriptions
PIN NUMBER 1 PIN NAME EN PIN DESCRIPTION Disables video inputs and outputs
EN
EQUIVALENT CIRCUIT
VSM CIRCUIT 1
2 3 4, 7, 10, 13, 16, 19, 22 5
VINA+ VINANC VSYNC
Non-inventing input Inverting input Not connected Vertical sync logic input
SYNC
VSM CIRCUIT 2
6 8 9 11 12 14 15 17 18 20 21 23 24
HSYNC VINB+ VINBVINC+ VINCVOUTCVOUTC+ VOUTB+ VOUTBVSVS+ VOUTAVOUTA+
Horizontal sync logic input Non-inverting input Inverting input Non-inverting input Inverting input Inverting output Non-inverting output Non-inverting output Inverting output Negative supply Positive supply Non-inverting output Inverting output
Reference Circuit 2
Typical Performance Curves
-42 BALANCE ERROR (dB) BLUE CM OUT (CH A) GREEN CM OUT (CH B) RED CM OUT (CH C) VSYNC HSYNC TIME (0.5ms/DIV) -62 100K 1M 10M 100M -46 -50 -54 -58 BALANCE ERROR= 20 LOG(VO,CM/VO,DIFF)
VOLTAGE (2.5V/DIV)
VOLTAGE (0.5V/DIV)
FREQUENCY (Hz)
FIGURE 1. COMMON MODE OUTPUT
FIGURE 2. BALANCE ERROR
4
EL4543 Typical Performance Curves
4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 -6 100K 1M 10M 100M 1G RL=50 RL=100 CL=0pF RL=500 NORMALIZED GAIN (dB) RL=200
(Continued)
4 3 2 1 0 -1 -2 -3 -4 -5 -6 100K 1M 10M 100M 1G 2.2pF RL=200 12pF 8.2pF 22pF
FREQUENCY RESPONSE (Hz)
FREQUENCY RESPONSE (Hz)
FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF
FIGURE 4. DIFFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF
4 3 NORMALIZED GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 -6 100K 1M 10M 100M 1G 2.2pF CMRR (dB) RL=100 CL=2.2pF 8.2pF 12pF 4.7pF 12pF
0 10 20 30 40 50 60 70 80 90 100 100K 1M 10M 100M 1G RL=200
FREQUENCY RESPONSE (Hz)
FREQUENCY RESPONSE (Hz)
FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF
FIGURE 6. CMRR
THRESHOLD (V) RELATIVE TO NEGATIVE SUPPLY
12 10 8 CMIR (V) 6 4 2 0 5 6 7 8 9 10 11 12 SUPPLY VOLAGE (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 5 6 7 8 9 10 11 12 VSWITCH
VSUPPLY (V)
FIGURE 7. COMMON MODE INPUT RANGE vs SUPPLY VOLTAGE
FIGURE 8. HSYNC & VSYNC THRESHOLD vs SUPPLY VOLTAGE
5
EL4543 Typical Performance Curves
-0 -10 -20 CURRENT (A) -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 0 10K 100K 1M 10M 100M FREQUENCY (Hz)
(Continued)
0.04 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 0 2 4 6 VOLTAGE (V) 8 RL=200 10 12
FIGURE 9. PSRR vs FREQUENCY
FIGURE 10. ISUPPLY vs VSUPPLY
3.5 ENABLE DISABLE PIN (V) 3 VOLTAGE (2V/DIV) 2.5 2 1.5 1 0.5 0 5 6 7 8 9 10 11 12 TIME (200ns/DIV) SUPPLY VOLTAGE (V) 2.5V 212ns ENABLE OUTPUT SIGNAL
FIGURE 11. ENABLE DISABLE vs SUPPLY VOLTAGE
FIGURE 12. ENABLE RESPONSE
2.5V
900ns
VOLTAGE (120mV/DIV)
DISABLE VOLTAGE (2V/DIV)
RL=200 DIFF CL=0pF
RISE t=25ns
FALL t=1.94ns
OUTPUT SIGNAL
TIME (200ns/DIV)
TIME (20ns/DIV)
FIGURE 13. DISABLE RESPONSE
FIGURE 14. DIFFERENTIAL SMALL SIGNAL TRANSIENT RESPONSE
6
EL4543 Typical Performance Curves
RL=200 DIFF CL=0pF VOLTAGE (235mV/DIV)
(Continued)
COMMON MODE DC LEVEL (V)
9 LOGIC HSYNC=0V 8V SYNC=0V 7 6 5 4 3 2 1 0 5 6 7 8 9 10
-B CM
CM
GR
EE
N
RISE t=2.81ns
FALL t=2.31ns
-A R
ED
E
C CM-
BLU
TIME (20ns/DIV)
11
12
SUPPLY VOLTAGE (V)
FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 16. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
9 COMMON MODE DC LEVEL (V) COMMON MODE DC LEVEL (V) LOGIC HSYNC=0V 8V SYNC=3V 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
D RE -A CM LUE -C B CM EEN B GR CM-
9
LOGIC HSYNC=3V 8 VSYNC=0V 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
C M -B GR EE N
-C CM
E BLU
CM-A
RED
FIGURE 17. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
FIGURE 18. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
9 COMMON MODE DC LEVEL (V) OUTPUT IMPEDANCE () LOGIC HSYNC=3V 8 VSYNC=3V 7 6 5 4 3 2 1 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V)
C M -C
50 AV=+2
BL UE
40 30 20 10 0 10K
ED AR CM EEN B GR C M-
100K
1M FREQUENCY (Hz)
10M
100M
FIGURE 19. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE
FIGURE 20. OUTPUT IMPEDANCE
7
EL4543 Typical Performance Curves
10K VOLTAGE NOISE (nV/Hz), CURRENT NOISE (pA/Hz)
(Continued)
0 RL=200 DIFF -20 CROSSTALK (dB)
1K
-40 -60 -80 -100 100K
100
10
1 10
100
1K
10K
100K
1M
10M
1M
10M FREQUENCY (Hz)
100M
400M
FREQUENCY (Hz)
FIGURE 21. INPUT VOLTAGE AND CURRENT NOISE
FIGURE 22. CHANNEL ISOLATION vs FREQUENCY
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 5 POWER DISSIPATION (W) NORMALIZED GAIN (dB) 3 1 -1 VOP-P=2V -3 -5 100K 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1M 10M FREQUENCY (Hz) 100M 1G 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
JA
1.087W
QS OP 24 15 C /W
VOP-P=200mV
=1
FIGURE 23. FREQUENCY RESPONSE vs OUTPUT AMPLITUDE
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.8 POWER DISSIPATION (W) 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
JA =
1.420W
QS OP 24 88 C /W
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
8
EL4543 and EL9110 CAT-5 SXGA Video Transmission
1 2 3 4 5 6
CAT1
CON8
CAT2
CON8
8 7 6 5 4 3 2 1
1 D 2
EN INA+ INAN.C.
EL4543 QSOP
OUTA+ OUTAN.C. VS+ VS-
24 23 22 21 20 19 18 17 16 15 14 13
RJOUTA+ 50
1 2 3 4 5 6 7 8
Red Out Differential
RJOUTA50
D
Red In
RJA+ 75
3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 4
VGAOUT
0.1uf CK5 +VS RD1 210 RD2 10K CD3 CAP 0.1uf CD1 RD5 75
Green In
5
RVSYNC 75
SYNC DECODER
1 2 3 4 5 Vout 1 Vin 1Vout 4 Vin 414 13 12 11 10 9 8 RD10 10K RD6 75 RD13 1K RD11 909 RD14 10K CD4 0.1uf
V-Sync Out Common Mode Green In
+VS
VSYNC
H-Sync Out
EL4543IU
RHSYNC 75
HSYNC N.C. INB+ INBN.C. INC+ INC-
N.C. OUTB+ OUTBN.C. OUTC+ OUTCN.C.
7 8
RJB+ 75
RJOUTB+ 50
+VS
Vin 1+ Vin 4+ Vs + Vs -
Green Out Differential
RJOUTB50 RJOUTC+ 50
Vin 3 + Vin 2 + Vin 3 - Vin 2 Vout 3 Vout 2
EL8401
6
6 RD3 10K RD4 10K 7 SOT-14
Common Mode Blue In
RD12 10K CO3
VGAIN
9 10
Blue Out
Green Out
RD7 10K
Red Out
UD1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CAP CO1 CO2 CAP CAP C
75 RBO
75 RGO
75 RRO
INDUCTOR IRON LB1
Red In Differential
50 RC1
Green In Differential
Blue In Differential
4.7uf CC1
INDUCTOR IRON LC1
B
INDUCTOR IRON LA1
EL9110
EL9110
4.7uf CC2 50 RC3 4.7uf CC3
10K RC4
CC4 1uf
0.1uf CC10
0.1uf CC11 +VS
RB3 50
4.7uf 4.7uf CB3 10K RB4
+VS 0.1uf CB10 0.1uf CB11
EL9110
9
C A
11
Blue Out Differential
RJOUTC50
Common Mode Red In
10K RD8 RD9 10K
Blue In
RJC+ 75
12
UJ1
EL4543
VCRTL RC5 330 CC8 1uf 5 16 15 14 13 12 11 10 9 VCRTL RB5 330 4.7uf RB1 CB1 50 CB2 CB8 1uf 5 16 15 14 13 12 11 10 9 VCRTL RA5 330 50 RA1 4.7uf CA1 10k RA2 CA8 1uf 5 16 15 14 13 12 11 10 9 B
10K RC2
1 2 3 4 5 6 7 8
UAC
Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
RC8
10K RB2
CB4 1uf
1 2 3 4 5 6 7 8
UAB
Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
RB8
UAA
1 2 3 4 5 6 7 8 Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref Cmext Vsp Enbl Vspo Vout Vsmo 0V X2
RA8
4.7uf CA2 50 RA3 4.7uf CA3
10K RA4
CA4 1uf
0.1uf CA10
0.1uf +VS CA11
EL9110 BLUE C
VGAN RC6 330 CC5 1uf 0.1uf CC12 LC2 INDUCTOR1 5 RC7 CC9 0.1uf +VS R21 RES1 R24 VGAN +VS R22 RES1 -VS VGAN RB6 330 CB5 1uf CB12 0.1uf
EL9110 GREEN B
LB2 INDUCTOR1 5 RB7 -VS VGAN RA6 330 CA5 1uf CB9 0.1uf +VS JP9 1 2 3 4 5 HEADER 5 + C1
4.7uf
EL9110 RED A
CA12 0.1uf LA2 INDUCTOR1 5 RA7 -VS
CC6 1uf
CB6 1uf
CA6 1uf
CA9 0.1uf
C3
0.1uF
A
R23
VCRTL
+ C2
4.7uf
C4
0.1uF
Title -VS Size:
EL4543 EL9110 System
Revision: Sheet of Drawn By: Kim Emanuel 6
Tab
#1
Date: 2/6/04 File: EL4543_9110_B.Sch 1 2 3 4 5
EL4543 Operational Description and Application Information
Introduction
The EL4543 is designed to differentially drive composite RGB video signals onto twisted pair lines, while simultaneously encoding horizontal and vertical sync signals as common mode output. The entire video signal plus sync can therefore be transmitted on 3 twisted pairs of wire. When utilizing CAT-5 cable, the 4th available twisted pair can be used for transmission of audio, data or control information. The distribution of composite video over standard CAT-5 cable enables enormous cost and labor savings compared with traditional coaxial cable, when considering both the relative low price and ease of pulling CAT-5 cable.
Sync Transmission
The EL4543 encodes HSYNC and VSYNC signals on the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figure 16, 17 and 18 clearly illustrate that the sum of the common mode voltages results in a fixed average DC level with no AC content and illustrates the logic levels. This eliminates EMI radiation into any common mode signal along the twisted pairs of CAT 5 cable.
Extract Common Mode Sync and Decode HSYNC & VSYNC
HSYNC and VSYNC can be regenerated from the Common Mode sync output voltages. The relationships between HSYNC, VSYNC and the 3 common mode levels are given by Table 1. The common mode levels are easily separated from the differential outputs of the EL4543 using this simple resistor network at the cable receiver input of each differential channel; see Figure 27.
Functional Description
The EL4543 provides three fully differential high-speed amplifiers, suitable for driving high-resolution composite video signals onto twisted pair or standard coaxial cable. The input common-mode range extends to the negative rail, allowing simple ground-referenced input termination to be used with a single supply. The amplifiers provide a fixed gain of +2 to compensate for standard video cable termination schemes. Horizontal and Vertical sync signals (HSYNC and VSYNC) are passed to an internal Logic Encoding Block to encode the sync information as three discrete signals of different voltage levels. Generally, in differential amplifiers an external VREF pin is used to control the common mode level of the differential output; in the case of the EL4543 the VREF of each of the three internal amplifier channels receives a signal from the Logic Encoding Block with encoded HSYNC and VSYNC information. The final output consists of three fully differential video signals, with sync encoded on the common mode of each of the three RGB differential signals. HSYNC and VSYNC can easily be separated from the differential output signals, decoded and transmitted along with the RGB video signals to the video monitor.
Twisted Pair Termination
The schematic in Figure 27 illustrates a termination scheme for 50 series termination and a 100 twisted pair cable. Note RCM is the common mode termination to allow measurement of VCM and should not be too small since it loads the EL4543; a little over a 100 is recommended for RCM.
TYPICAL EL4543 TERMINATION DRIVER 50 + 50 VREF TWISTED PAIR ZO =100 + 50 VCM 50 120 (RCM: SHOULD BE >100) (FOR LOADING CONSIDERATIONS)
FIGURE 27. TWISTED PAIR TERMINATION EL4543
Video Transmission
The EL4543 is a twisted pair differential line driver directed at the transmission of Video Signals through cables up to 100 feet; however, as signal losses increase with transmission line length the EL4543 will need additional support to equalize video signals along longer twisted pair transmission lines. A full solution to accomplish this is the SXGA Video Transmission System presented in the EL4543 Data Sheet. Note the inclusion of the EL9110 for signal equalization of up to 1000ft of CAT-5 cable and common mode extraction; see Data Sheet for additional information on the EL9110.
ENABLE/DISABLE
+ INA -
EN + VREF
+ OUTA -
VSYNC HSYNC EN LOGIC DECODING
RCM GCM BCM
+ INB -
EN + VREF
+ OUTB -
Long Distance Video Transmission
+ INC EN + VREF + OUTC -
FIGURE 26. BLOCK DIAGRAM EL4543
The SXGA Video Transmission System makes it possible to transmit Red, Green and Blue (RGB) video plus sync up to 1000 feet through CAT-5 cable. The input to the SXGA Video Transmission System is the output of a video source transmitting RGB video signals plus sync. The signals are received initially by the EL4543; which converts the single
10
EL4543
ended input RGB signals to three fully differential waveforms with sync encoded on the discrete common modes of each color channel and then drives the signals through a length of CAT-5 cable. The signal is received by the EL9110, which can provide 6-pole equalization for both high and low frequency signal transmission line losses. Then the EL9110 converts the differential RGB video signals back into single ended format while extracting the common mode component for decoding. The single ended RGB signal is taken directly from the output of the El9110 and is ready for the output device. The Common Mode Decoder Circuit receives the common mode signals directly from each of the three EL9110's common mode output pin, decodes and transmits HSYNC and VSYNC to the output device.
Proper Layout Technique
A critical concern with any PCB layout is the establishment of a "healthy" ground plane. It is imperative to provide ground planes terminated close to inputs to minimize input capacitance. Additionally, the ground plane can be selectively removed from inputs to prevent load and supply currents from flowing near the input nodes. In general the following guidelines apply to all PCB layout: * Keep all traces as short as possible. * Keep power supply bypass components as close to the chip as possible - extremely close. * Create a healthy ground with low impedance and continuous ground pathways available to all grounded components board-wide. * In high frequency applications on multi-level boards try to keep one level of board with continuous ground plane and minimum via cutouts - providing it is affordable. * Provide extremely short loops from power pin to ground. * If it is affordable, a ferrite bead is always of benefit to isolate device from Power Supply noise and the rest of the circuit from the noise of the device.
Sync Transmission
The EL4543 encodes HSYNC and VSYNC signals onto the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figure 8 clearly illustrates that the sum of the common mode voltages results in a fixed DC level with no AC content; thus eliminating EMI interference.
Output Drive Protection
The EL4543 has internal short circuit protection set typically at 60mA. if the output is shorted for extended periods of time the increased power dissipation will eventually destroy the part. To realize maximum reliability the output current should never exceed 60mA. The 50 series back load matching resistor provides additional protection.
Power Dissipation Calculation
When switching at high speeds, or driving heavy loads, the EL4543 drive capability is ultimately limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated:
4 2 2 PD = ( V S x I S ) x ( C INT x V S x f ) + ( C L x V OUT x f ) 1
Supply Voltage
While the EL4543 can be operated on 5V split rails, single supply 0V to 5V is the most common usage. It is very important to note that the input logic thresholds are relative to the negative supply pin, and therefore single supply, ground referenced logic will not work when driving the EL4543 on split rails. The amplifiers have an input common mode range from 1.5V to 3.5V with a 0V to 5V supply. The common mode output DC level range is a linear function of the power supply, see Data Sheet Figures 15, 16, 17 &18. The common mode input switching threshold as well as the Enable/Disable input is a linear function of the supply voltage, see Data Sheet Figure 1.
where: * VS is the total power supply to the EL4543 (from VS+ to VS-) * VOUT is the swing on the output (VH - VL) * CL is the load capacitance * CINT is the internal load capacitance (80pF max) * IS is the quiescent supply current (40mA max) * f is frequency Having obtained the application's power dissipation, the maximum junction temperature can be calculated:
T JMAX = T MAX + JA x PD
Disable and Power Down
The EL4543 provides an enable disable function which powers down, logic input high, in 900ns and powers up, logic input low, in 212ns. Disabled the amplifiers supply current is reduced to 1.8mA (Positive Supply) and 0mA (Negative Supply). Note that Enable/Disable threshold is a linear function of the supply voltage levels. The Enable/Disable threshold voltage level is compatible with standard TTL/CMOS and referenced to the lowest supply potential.
where: * TJMAX is the maximum junction temperature (125C) * TMAX is the maximum ambient operating temperature * PD is the power dissipation calculated above * JA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves.
11
EL4543 QSOP Package Outline Drawing
12
EL4543 QFN Package Outline Drawing
NOTE: The package drawings shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13

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